/*
* emulates the DCPU16 system from http://0x10c.com/doc/dcpu-16.txt
+ * currently emulates '1.7' spec from http://pastebin.com/Q4JvQvnM
*
* I couldn't remember ever implementing an emulator before, so this
* happened. As such, consider this a toy in progress.
* !! v1.7 hardware interface needs to be finished
* !! v1.7 interrupts need to be finished
* change api to print into buffers rather than stdio
- * refactor opcode functiontables into switch statements
* let callbacks determine whether to override events, or just observe
* sort init callbacks by base addr, to call in-order
* make all callbacks register addr range of interest
return message;
}
+inline
+void dcpu16_cycle_inc(struct dcpu16 *vm, unsigned int n) {
+ size_t i;
+
+ while (n--) {
+ /* new cycle */
+ vm->cycle_ += 1;
+ TRACE("%s>> starting cycle %llu", vm->cycle_);
+
+ /* signal interested cycle hooks */
+ acct_event_(vm, DCPU16_ACCT_EV_CYCLE, vm->reg[DCPU16_REG_PC]);
+
+ /* signal attached hardware */
+ for (i = 0; i < vm->hw_table_entries_; i++) {
+ TRACE("%s>> notifying %s", __func__, vm->hw_table_[i].name_);
+ vm->hw_table_[i].cycle(vm, vm->hw_table_[i].data);
+ }
+ }
+}
+
/* value_decode_
* sets *v to be the address of the represented value
* value_is_a is 0 for b, 1 for a, alters behavior of some operands
&vm->reg_work_[1], &a, &ev_a_addr,\
&pc_adjust, &sp_adjust, &cycle_adjust);\
vm->reg[DCPU16_REG_SP] += sp_adjust;\
- vm->cycle += cycle_adjust;\
+ dcpu16_cycle_inc(vm, cycle_adjust);\
} while (0)
#define OP_NBI_ (void)val_b, (void)b, (void)ev_b_addr, (void)val_b_data
#define OP_BASIC_ value_decode_(vm, val_b, 0, val_b_data,\
vm->ram[ --vm->reg[DCPU16_REG_SP] ] = vm->reg[DCPU16_REG_PC];
vm->reg[DCPU16_REG_PC] = *a;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(vm->reg[DCPU16_REG_SP] + 1);
}
vm->reg[0] = *a;
}
- vm->cycle += 4;
+ dcpu16_cycle_inc(vm, 4);
}
OP_IMPL(nbi_iag) {
*a = vm->reg[DCPU16_REG_IA];
+ dcpu16_cycle_inc(vm, 1);
+
ACCT_W(ev_a_addr);
}
vm->reg[DCPU16_REG_IA] = *a;
+ dcpu16_cycle_inc(vm, 1);
+
ACCT_R(ev_a_addr);
}
vm->interrupts_deferred_ = 0;
vm->reg[DCPU16_REG_A] = vm->ram[vm->reg[DCPU16_REG_SP]++];
vm->reg[DCPU16_REG_PC] = vm->ram[vm->reg[DCPU16_REG_SP]++];
+
+ dcpu16_cycle_inc(vm, 3);
}
OP_IMPL(nbi_iaq) {
vm->interrupts_deferred_ = 0;
}
+ dcpu16_cycle_inc(vm, 2);
+
ACCT_R(ev_a_addr);
}
*a = vm->hw_table_entries_;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(nbi_hwq) {
vm->reg[DCPU16_REG_X] = vm->hw_table_[*a].mfg_l;
vm->reg[DCPU16_REG_Y] = vm->hw_table_[*a].mfg_h;
- vm->cycle += 4;
+ dcpu16_cycle_inc(vm, 4);
}
OP_IMPL(nbi_hwi) {
return;
}
- vm->cycle += 4;
+ dcpu16_cycle_inc(vm, 4);
if (vm->hw_table_[*a].hwi)
vm->hw_table_[*a].hwi(vm, vm->hw_table_[*a].data);
else
vm->on_fire_ = 1;
WARN("system on fire");
- vm->cycle += 9;
+ dcpu16_cycle_inc(vm, 9);
}
static const struct opcode_entry opcode_nbi_entries[] = {
*/
*b = *a;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
ACCT_W(ev_b_addr);
}
*b = acc;
vm->reg[DCPU16_REG_EX] = (acc > 0xffff);
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
*b = acc;
vm->reg[DCPU16_REG_EX] = (acc > 0xffff);
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
*b = acc;
vm->reg[DCPU16_REG_EX] = acc >> 16;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
*b = acc;
vm->reg[DCPU16_REG_EX] = acc >> 16;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
vm->reg[DCPU16_REG_EX] = (*b << 16) / *a;
}
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
vm->reg[DCPU16_REG_EX] = (short)(*b << 16) / (short)*a;
}
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
*b = *b % *a;
}
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_a_addr);
}
*b = (short)*b % (short)*a;
}
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
*b = *b & *a;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
ACCT_W(ev_b_addr);
}
*b = *b | *a;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
ACCT_W(ev_b_addr);
}
*b = *b ^ *a;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
ACCT_W(ev_b_addr);
}
*b = acc & 0xffff;
vm->reg[DCPU16_REG_EX] = (*b << 16) >> *a;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
WARN("IMPLEMENT");
*b = acc & 0xffff;
vm->reg[DCPU16_REG_EX] = (*b << 16) >> *a;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
WARN("IMPLEMENT");
vm->reg[DCPU16_REG_EX] = acc >> 16;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifc) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ife) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifn) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle++;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifg) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle++;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifa) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifl) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle++;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifu) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(adx) {
else
vm->reg[DCPU16_REG_EX] = 0x0000;
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
else
vm->reg[DCPU16_REG_EX] = 0;
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
vm->reg[DCPU16_REG_I] += 1;
vm->reg[DCPU16_REG_J] += 1;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
vm->reg[DCPU16_REG_I] -= 1;
vm->reg[DCPU16_REG_J] -= 1;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
/* execute the next instruction */
void dcpu16_step(struct dcpu16 *vm) {
DCPU16_WORD opcode, b, a, instr_len, *b_data, *a_data;
- size_t i;
const struct opcode_entry *e;
if (!vm)
return;
- /* signal interested parties that a new cycle has ticked */
- TRACE("%s>> sending global cycle event", __func__);
- acct_event_(vm, DCPU16_ACCT_EV_CYCLE, vm->reg[DCPU16_REG_PC]);
-
- /* signal attached hardware */
- for (i = 0; i < vm->hw_table_entries_; i++) {
- if (vm->hw_table_[i].cycle) {
- TRACE("%s>> sending cycle to %s", __func__, vm->hw_table_[i].name_);
- vm->hw_table_[i].cycle(vm, vm->hw_table_[i].data);
- }
- }
-
instruction_decode_(vm->ram, vm->reg[DCPU16_REG_PC], &opcode, &b, &b_data, &a, &a_data, &instr_len);
/* consume what we decoded */
TRACE("++ SKIPPED %x words", instr_len);
if (opcode >= 0x10 && opcode <= 0x17) {
/* skipping a branch instruction? skip branch's skippable instruction as well */
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
} else {
vm->skip_ = 0;
}
DCPU16_WORD message;
message = interrupt_dequeue_(vm);
+ TRACE("%s>> %s interrupt IA:0x%04x message:0x%04x",
+ __func__,
+ vm->reg[DCPU16_REG_IA] ? "servicing" : "ignoring",
+ vm->reg[DCPU16_REG_IA],
+ message);
if (vm->reg[DCPU16_REG_IA]) {
- TRACE("%s>> servicing interrupt IA:0x%04x message:0x%04x \n", __func__, vm->reg[DCPU16_REG_IA], message);
/* then service the next interrupt */
vm->interrupts_deferred_ = 1;
vm->ram[--vm->reg[DCPU16_REG_SP]] = vm->reg[DCPU16_REG_PC];
vm->ram[--vm->reg[DCPU16_REG_SP]] = vm->reg[DCPU16_REG_A];
vm->reg[DCPU16_REG_PC] = vm->reg[DCPU16_REG_IA];
vm->reg[DCPU16_REG_A] = message;
- } else {
- TRACE("%s>> ignoring interrupt IA:0", __func__);
}
}
}
printf("\n");
printf("(0x%08llx) %2s:0x%04x %2s:0x%04x %2s:0x%04x %2s:0x%04x [%2s]:",
- vm->cycle,
+ vm->cycle_,
dcpu16_reg_names[DCPU16_REG_EX], vm->reg[DCPU16_REG_EX],
dcpu16_reg_names[DCPU16_REG_SP], vm->reg[DCPU16_REG_SP],
dcpu16_reg_names[DCPU16_REG_PC], vm->reg[DCPU16_REG_PC],
memset(vm->reg, 0, sizeof vm->reg);
memset(vm->ram, 0, sizeof vm->ram);
- vm->cycle = 0;
+ vm->cycle_ = 0;
acct_event_(vm, DCPU16_ACCT_EV_RESET, 0);
}
projects / dcpu16 / blobdiff