/*
* emulates the DCPU16 system from http://0x10c.com/doc/dcpu-16.txt
+ * currently emulates '1.7' spec from http://pastebin.com/Q4JvQvnM
*
* I couldn't remember ever implementing an emulator before, so this
* happened. As such, consider this a toy in progress.
* !! v1.7 hardware interface needs to be finished
* !! v1.7 interrupts need to be finished
* change api to print into buffers rather than stdio
- * refactor opcode functiontables into switch statements
* let callbacks determine whether to override events, or just observe
* sort init callbacks by base addr, to call in-order
* make all callbacks register addr range of interest
return message;
}
+inline
+void dcpu16_cycle_inc(struct dcpu16 *vm, unsigned int n) {
+ size_t i;
+
+ while (n--) {
+ /* new cycle */
+ vm->cycle_ += 1;
+ TRACE("%s>> starting cycle %llu", vm->cycle_);
+
+ /* signal interested cycle hooks */
+ acct_event_(vm, DCPU16_ACCT_EV_CYCLE, vm->reg[DCPU16_REG_PC]);
+
+ /* signal attached hardware */
+ for (i = 0; i < vm->hw_table_entries_; i++) {
+ TRACE("%s>> notifying %s", __func__, vm->hw_table_[i].mod->name_);
+ if (vm->hw_table_[i].mod->cycle)
+ vm->hw_table_[i].mod->cycle(vm, &vm->hw_table_[i]);
+ }
+ }
+}
+
/* value_decode_
* sets *v to be the address of the represented value
* value_is_a is 0 for b, 1 for a, alters behavior of some operands
assert(value <= 0x3f);
DCPU16_WORD pc = (DCPU16_WORD)(vm->reg[DCPU16_REG_PC] + *pc_adjust),
- sp = (DCPU16_WORD)(vm->reg[DCPU16_REG_PC] + *sp_adjust);
+ sp = (DCPU16_WORD)(vm->reg[DCPU16_REG_SP] + *sp_adjust);
- TRACE("%s: pc:0x%04x sp:0x%04x value_data:0x%04x\n",
+ TRACE("%s>> is_a:%u pc:0x%04x sp:0x%04x value_data:0x%04x\n",
__func__,
+ value_is_a,
pc,
sp,
value_data);
&vm->reg_work_[1], &a, &ev_a_addr,\
&pc_adjust, &sp_adjust, &cycle_adjust);\
vm->reg[DCPU16_REG_SP] += sp_adjust;\
- vm->cycle += cycle_adjust;\
+ dcpu16_cycle_inc(vm, cycle_adjust);\
} while (0)
#define OP_NBI_ (void)val_b, (void)b, (void)ev_b_addr, (void)val_b_data
#define OP_BASIC_ value_decode_(vm, val_b, 0, val_b_data,\
vm->ram[ --vm->reg[DCPU16_REG_SP] ] = vm->reg[DCPU16_REG_PC];
vm->reg[DCPU16_REG_PC] = *a;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(vm->reg[DCPU16_REG_SP] + 1);
}
vm->reg[0] = *a;
}
- vm->cycle += 4;
+ dcpu16_cycle_inc(vm, 4);
}
OP_IMPL(nbi_iag) {
*a = vm->reg[DCPU16_REG_IA];
+ dcpu16_cycle_inc(vm, 1);
+
ACCT_W(ev_a_addr);
}
vm->reg[DCPU16_REG_IA] = *a;
+ dcpu16_cycle_inc(vm, 1);
+
ACCT_R(ev_a_addr);
}
vm->interrupts_deferred_ = 0;
vm->reg[DCPU16_REG_A] = vm->ram[vm->reg[DCPU16_REG_SP]++];
vm->reg[DCPU16_REG_PC] = vm->ram[vm->reg[DCPU16_REG_SP]++];
+
+ dcpu16_cycle_inc(vm, 3);
}
OP_IMPL(nbi_iaq) {
vm->interrupts_deferred_ = 0;
}
+ dcpu16_cycle_inc(vm, 2);
+
ACCT_R(ev_a_addr);
}
*a = vm->hw_table_entries_;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(nbi_hwq) {
return;
}
- vm->reg[DCPU16_REG_A] = vm->hw_table_[*a].id_l;
- vm->reg[DCPU16_REG_B] = vm->hw_table_[*a].id_h;
- vm->reg[DCPU16_REG_C] = vm->hw_table_[*a].ver;
- vm->reg[DCPU16_REG_X] = vm->hw_table_[*a].mfg_l;
- vm->reg[DCPU16_REG_Y] = vm->hw_table_[*a].mfg_h;
+ vm->reg[DCPU16_REG_A] = vm->hw_table_[*a].mod->id_l;
+ vm->reg[DCPU16_REG_B] = vm->hw_table_[*a].mod->id_h;
+ vm->reg[DCPU16_REG_C] = vm->hw_table_[*a].mod->ver;
+ vm->reg[DCPU16_REG_X] = vm->hw_table_[*a].mod->mfg_l;
+ vm->reg[DCPU16_REG_Y] = vm->hw_table_[*a].mod->mfg_h;
- vm->cycle += 4;
+ dcpu16_cycle_inc(vm, 4);
}
OP_IMPL(nbi_hwi) {
return;
}
- vm->cycle += 4;
- if (vm->hw_table_[*a].hwi)
- vm->hw_table_[*a].hwi(vm, vm->hw_table_[*a].data);
+ dcpu16_cycle_inc(vm, 4);
+ if (vm->hw_table_[*a].mod->hwi)
+ vm->hw_table_[*a].mod->hwi(vm, &vm->hw_table_[*a]);
else
WARN("hardware 0x%04x has no interrupt handler", *a);
}
vm->on_fire_ = 1;
WARN("system on fire");
- vm->cycle += 9;
+ dcpu16_cycle_inc(vm, 9);
}
static const struct opcode_entry opcode_nbi_entries[] = {
*/
*b = *a;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
ACCT_W(ev_b_addr);
}
*b = acc;
vm->reg[DCPU16_REG_EX] = (acc > 0xffff);
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
*b = acc;
vm->reg[DCPU16_REG_EX] = (acc > 0xffff);
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
*b = acc;
vm->reg[DCPU16_REG_EX] = acc >> 16;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
*b = acc;
vm->reg[DCPU16_REG_EX] = acc >> 16;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
vm->reg[DCPU16_REG_EX] = (*b << 16) / *a;
}
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
vm->reg[DCPU16_REG_EX] = (short)(*b << 16) / (short)*a;
}
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
*b = *b % *a;
}
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_a_addr);
}
*b = (short)*b % (short)*a;
}
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
*b = *b & *a;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
ACCT_W(ev_b_addr);
}
*b = *b | *a;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
ACCT_W(ev_b_addr);
}
*b = *b ^ *a;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
ACCT_W(ev_b_addr);
}
*b = acc & 0xffff;
vm->reg[DCPU16_REG_EX] = (*b << 16) >> *a;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
WARN("IMPLEMENT");
*b = acc & 0xffff;
vm->reg[DCPU16_REG_EX] = (*b << 16) >> *a;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
WARN("IMPLEMENT");
vm->reg[DCPU16_REG_EX] = acc >> 16;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifc) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ife) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifn) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle++;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifg) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle++;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifa) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifl) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle++;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(ifu) {
/* */
} else {
vm->skip_ = 1;
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
}
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
}
OP_IMPL(adx) {
else
vm->reg[DCPU16_REG_EX] = 0x0000;
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
else
vm->reg[DCPU16_REG_EX] = 0;
- vm->cycle += 3;
+ dcpu16_cycle_inc(vm, 3);
ACCT_W(ev_b_addr);
}
vm->reg[DCPU16_REG_I] += 1;
vm->reg[DCPU16_REG_J] += 1;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
vm->reg[DCPU16_REG_I] -= 1;
vm->reg[DCPU16_REG_J] -= 1;
- vm->cycle += 2;
+ dcpu16_cycle_inc(vm, 2);
ACCT_W(ev_b_addr);
}
*a = (mem[addr] >> (OPCODE_BASIC_BITS + OPCODE_OPERAND_B_BITS)) & ((1 << OPCODE_OPERAND_A_BITS) - 1);
*instr_len = 1;
- if ( (*b >= 0x10 && *b <= 0x17) || *b == 0x1e || *b == 0x1f ) {
+ if ((*opcode != 0x0000) &&
+ ( (*b >= 0x10 && *b <= 0x17) || *b == 0x1e || *b == 0x1f ) ) {
*b_data = mem + (DCPU16_WORD)(addr + *instr_len);
- TRACE("**b_data:%hu", **b_data);
*instr_len += 1;
} else {
*b_data = NULL;
if ( (*opcode != 0x0000 || (*opcode == 0 && *b != 0x0000) )
&& ( (*a >= 0x10 && *a <= 0x17) || *a == 0x1e || *a == 0x1f) ) {
*a_data = mem + (DCPU16_WORD)(addr + *instr_len);
- TRACE("**a_data:%hu", **a_data);
*instr_len += 1;
} else {
*a_data = NULL;
}
-#if 0
TRACE("\n%s: [0x%04x]:0x%04x op:0x%02x b:0x%02x (b_data:0x%04x) a:0x%02x (a_data:0x%04x) len:0x%02x\n",
__func__,
addr,
*a,
*a_data ? **a_data : 0,
*instr_len);
-#endif
}
/* dcpu16_mnemonify_buf
/* execute the next instruction */
void dcpu16_step(struct dcpu16 *vm) {
DCPU16_WORD opcode, b, a, instr_len, *b_data, *a_data;
- size_t i;
const struct opcode_entry *e;
- if (!vm) return;
-
- /* signal interested parties that a new cycle has ticked */
- TRACE("%s: sending global cycle event", __func__);
- acct_event_(vm, DCPU16_ACCT_EV_CYCLE, vm->reg[DCPU16_REG_PC]);
-
- /* signal attached hardware */
- for (i = 0; i < vm->hw_table_entries_; i++) {
- if (vm->hw_table_[i].cycle) {
- TRACE("%s: sending cycle to %s", __func__, vm->hw_table_[i].name_);
- vm->hw_table_[i].cycle(vm, vm->hw_table_[i].data);
- }
- }
+ if (!vm)
+ return;
instruction_decode_(vm->ram, vm->reg[DCPU16_REG_PC], &opcode, &b, &b_data, &a, &a_data, &instr_len);
TRACE("++ SKIPPED %x words", instr_len);
if (opcode >= 0x10 && opcode <= 0x17) {
/* skipping a branch instruction? skip branch's skippable instruction as well */
- vm->cycle += 1;
+ dcpu16_cycle_inc(vm, 1);
} else {
vm->skip_ = 0;
}
DCPU16_WORD message;
message = interrupt_dequeue_(vm);
+ TRACE("%s>> %s interrupt IA:0x%04x message:0x%04x",
+ __func__,
+ vm->reg[DCPU16_REG_IA] ? "servicing" : "ignoring",
+ vm->reg[DCPU16_REG_IA],
+ message);
if (vm->reg[DCPU16_REG_IA]) {
- TRACE("servicing interrupt IA:0x%04x message:0x%04x \n", vm->reg[DCPU16_REG_IA], message);
/* then service the next interrupt */
vm->interrupts_deferred_ = 1;
vm->ram[--vm->reg[DCPU16_REG_SP]] = vm->reg[DCPU16_REG_PC];
vm->ram[--vm->reg[DCPU16_REG_SP]] = vm->reg[DCPU16_REG_A];
vm->reg[DCPU16_REG_PC] = vm->reg[DCPU16_REG_IA];
vm->reg[DCPU16_REG_A] = message;
- } else {
- TRACE("ignoring interrupt IA:0");
}
}
}
}
-/*
- print the current state of the machine
- shows current cycle count, registers, and next instruction
-*/
-void dcpu16_state_print(struct dcpu16 *vm) {
- unsigned int i;
- if (!vm) return;
+/* instantiate a new 'hardware' device */
+struct dcpu16_hw *dcpu16_hw_new(struct dcpu16 *vm, struct dcpu16_hw_module *mod, void *data) {
+ struct dcpu16_hw *hw;
- printf(" ");
- for (i = 0; i < 8; i++)
- printf(" %s:0x%04x", dcpu16_reg_names[i], vm->reg[i]);
- printf("\n");
+ hw = malloc(sizeof *hw);
+ if (hw == NULL) {
+ vm->warn_cb_("%s():%s", "malloc", strerror(errno));
+ return NULL;
+ }
+ hw->vm = vm;
+ hw->mod = mod;
+
+ if (mod->data_init) {
+ if (mod->data_init(hw, data)) {
+ vm->warn_cb_("failed to init hw module data");
+ free(hw);
+ return NULL;
+ }
+ } else {
+ hw->data = NULL;
+ }
- printf("(0x%08llx) %2s:0x%04x %2s:0x%04x %2s:0x%04x %2s:0x%04x [%2s]:",
- vm->cycle,
- dcpu16_reg_names[DCPU16_REG_EX], vm->reg[DCPU16_REG_EX],
- dcpu16_reg_names[DCPU16_REG_SP], vm->reg[DCPU16_REG_SP],
- dcpu16_reg_names[DCPU16_REG_PC], vm->reg[DCPU16_REG_PC],
- dcpu16_reg_names[DCPU16_REG_IA], vm->reg[DCPU16_REG_IA],
- "PC");
+ return hw;
+}
- dcpu16_disassemble_print(vm, vm->reg[DCPU16_REG_PC]);
- printf("\n");
+/* destroy a 'hardware' device */
+void dcpu16_hw_del(struct dcpu16_hw **hw) {
+ if (hw) {
+ if (*hw) {
+ if ((*hw)->mod->data_free) {
+ (*hw)->mod->data_free(*hw);
+ }
+ free(*hw);
+ *hw = NULL;
+ }
+ }
}
-/* dcpu16_dump_ram
- * print raw ram contents from start to stop
+/* dcpu16_hw_ctl
+ * invokes per-module controls for hw device
*/
-void dcpu16_dump_ram(struct dcpu16 *vm, DCPU16_WORD start, DCPU16_WORD end) {
- unsigned int i, j;
- const unsigned int n = 8; /* words per line */
-
- if (!vm) return;
-
- for (i = start, j = 0; i <= end; i++, j++) {
- if (j % n == 0)
- printf("0x%04x:\t", i);
- printf(" %04x%s", vm->ram[i], (j % n) == (n - 1) ? "\n" : "");
+int dcpu16_hw_ctl(struct dcpu16_hw *hw, const char *cmd, void *data_in, void *data_out) {
+ if (hw) {
+ if (hw->mod) {
+ if (hw->mod->ctl) {
+ if (cmd) {
+ return hw->mod->ctl(hw, cmd, data_in, data_out);
+ }
+ }
+ }
}
- if ((j % n) != (n - 1))
- printf("\n");
+ return 0;
}
-/* dcpu16_hw_add
+
+/* dcpu16_hw_attach
* registers new 'hardware' device with system
*/
-int dcpu16_hw_add(struct dcpu16 *vm, struct dcpu16_hw *hw) {
+int dcpu16_hw_attach(struct dcpu16 *vm, struct dcpu16_hw *hw) {
if (!vm || !hw)
return -1;
+ TRACE("%s>> name:%s ID:0x%04x%04x MFG:0x%04x%04x VER:0x%04x",
+ __func__,
+ hw->mod->name_,
+ hw->mod->id_h, hw->mod->id_l,
+ hw->mod->mfg_l, hw->mod->mfg_h,
+ hw->mod->ver);
+
if (vm->hw_table_entries_ == 0xffff) {
WARN("maximum hardware entries reached");
return -1;
memcpy(vm->hw_table_ + vm->hw_table_entries_, hw, sizeof *hw);
vm->hw_table_entries_++;
+ TRACE("%s>> added hw entry %zu", __func__, vm->hw_table_entries_);
+
return 0;
}
memcpy(vm->cb_table_ + vm->cb_table_entries_, &cb, sizeof cb);
vm->cb_table_entries_++;
+ TRACE("%s>> attached event callback %zu", __func__, vm->cb_table_entries_);
+
return 0;
}
if (!vm)
return;
+ TRACE("%s>> reset", __func__);
+
vm->skip_ = 0;
vm->interrupts_deferred_ = 0;
vm->on_fire_ = 0;
/* signal attached hardware */
for (i = 0; i < vm->hw_table_entries_; i++) {
- if (vm->hw_table_[i].reset)
- vm->hw_table_[i].reset(vm, vm->hw_table_[i].data);
+ if (vm->hw_table_[i].mod->reset)
+ vm->hw_table_[i].mod->reset(vm, &vm->hw_table_[i]);
}
memset(vm->reg, 0, sizeof vm->reg);
memset(vm->ram, 0, sizeof vm->ram);
- vm->cycle = 0;
+ vm->cycle_ = 0;
acct_event_(vm, DCPU16_ACCT_EV_RESET, 0);
}
projects / dcpu16 / blobdiff