-In a basic instruction, the lower four bits of the first word of the instruction are the opcode,\r
-and the remaining twelve bits are split into two six bit values, called a and b.\r
-a is always handled by the processor before b, and is the lower six bits.\r
-In bits (with the least significant being last), a basic instruction has the format: bbbbbbaaaaaaoooo\r
-\r
-\r
-\r
-Values: (6 bits)\r
- 0x00-0x07: register (A, B, C, X, Y, Z, I or J, in that order)\r
- 0x08-0x0f: [register]\r
- 0x10-0x17: [next word + register]\r
- 0x18: POP / [SP++]\r
- 0x19: PEEK / [SP]\r
- 0x1a: PUSH / [--SP]\r
- 0x1b: SP\r
- 0x1c: PC\r
- 0x1d: O\r
- 0x1e: [next word]\r
- 0x1f: next word (literal)\r
- 0x20-0x3f: literal value 0x00-0x1f (literal)\r
- \r
-* "next word" really means "[PC++]". These increase the word length of the instruction by 1. \r
-* If any instruction tries to assign a literal value, the assignment fails silently. Other than that, the instruction behaves as normal.\r
-* All values that read a word (0x10-0x17, 0x1e, and 0x1f) take 1 cycle to look up. The rest take 0 cycles.\r
-* By using 0x18, 0x19, 0x1a as POP, PEEK and PUSH, there's a reverse stack starting at memory location 0xffff. Example: "SET PUSH, 10", "SET X, POP"\r
-\r
-\r
-\r
-Basic opcodes: (4 bits)\r
- 0x0: non-basic instruction - see below\r
- 0x1: SET a, b - sets a to b\r
- 0x2: ADD a, b - sets a to a+b, sets O to 0x0001 if there's an overflow, 0x0 otherwise\r
- 0x3: SUB a, b - sets a to a-b, sets O to 0xffff if there's an underflow, 0x0 otherwise\r
- 0x4: MUL a, b - sets a to a*b, sets O to ((a*b)>>16)&0xffff\r
- 0x5: DIV a, b - sets a to a/b, sets O to ((a<<16)/b)&0xffff. if b==0, sets a and O to 0 instead.\r
- 0x6: MOD a, b - sets a to a%b. if b==0, sets a to 0 instead.\r
- 0x7: SHL a, b - sets a to a<<b, sets O to ((a<<b)>>16)&0xffff\r
- 0x8: SHR a, b - sets a to a>>b, sets O to ((a<<16)>>b)&0xffff\r
- 0x9: AND a, b - sets a to a&b\r
- 0xa: BOR a, b - sets a to a|b\r
- 0xb: XOR a, b - sets a to a^b\r
- 0xc: IFE a, b - performs next instruction only if a==b\r
- 0xd: IFN a, b - performs next instruction only if a!=b\r
- 0xe: IFG a, b - performs next instruction only if a>b\r
- 0xf: IFB a, b - performs next instruction only if (a&b)!=0\r
- \r
-* SET, AND, BOR and XOR take 1 cycle, plus the cost of a and b\r
-* ADD, SUB, MUL, SHR, and SHL take 2 cycles, plus the cost of a and b\r
-* DIV and MOD take 3 cycles, plus the cost of a and b\r
-* IFE, IFN, IFG, IFB take 2 cycles, plus the cost of a and b, plus 1 if the test fails\r
- \r
+In a basic instruction, the lower five bits of the first word of the instruction\r
+are the opcode, and the remaining eleven bits are split into a five bit value b\r
+and a six bit value a.\r
+b is always handled by the processor after a, and is the lower five bits.\r
+In bits (in LSB-0 format), a basic instruction has the format: aaaaaabbbbbooooo\r
+\r
+In the tables below, C is the time required in cycles to look up the value, or\r
+perform the opcode, VALUE is the numerical value, NAME is the mnemonic, and\r
+DESCRIPTION is a short text that describes the opcode or value.\r
+\r
+\r
+\r
+--- Values: (5/6 bits) ---------------------------------------------------------\r
+ C | VALUE | DESCRIPTION\r
+---+-----------+----------------------------------------------------------------\r
+ 0 | 0x00-0x07 | register (A, B, C, X, Y, Z, I or J, in that order)\r
+ 0 | 0x08-0x0f | [register]\r
+ 1 | 0x10-0x17 | [register + next word]\r
+ 0 | 0x18 | (PUSH / [--SP]) if in b, or (POP / [SP++]) if in a\r
+ 0 | 0x19 | [SP] / PEEK\r
+ 1 | 0x1a | [SP + next word] / PICK n\r
+ 0 | 0x1b | SP\r
+ 0 | 0x1c | PC\r
+ 0 | 0x1d | EX\r
+ 1 | 0x1e | [next word]\r
+ 1 | 0x1f | next word (literal)\r
+ 0 | 0x20-0x3f | literal value 0xffff-0x1e (-1..30) (literal) (only for a)\r
+ --+-----------+----------------------------------------------------------------\r
+ \r
+* "next word" means "[PC++]". Increases the word length of the instruction by 1.\r
+* By using 0x18, 0x19, 0x1a as PEEK, POP/PUSH, and PICK there's a reverse stack\r
+ starting at memory location 0xffff. Example: "SET PUSH, 10", "SET X, POP"\r
+* Attempting to write to a literal value fails silently\r
+\r
+\r
+\r
+--- Basic opcodes (5 bits) ----------------------------------------------------\r
+ C | VAL | NAME | DESCRIPTION\r
+---+------+----------+---------------------------------------------------------\r
+ - | 0x00 | n/a | special instruction - see below\r
+ 1 | 0x01 | SET b, a | sets b to a\r
+ 2 | 0x02 | ADD b, a | sets b to b+a, sets EX to 0x0001 if there's an overflow, \r
+ | | | 0x0 otherwise\r
+ 2 | 0x03 | SUB b, a | sets b to b-a, sets EX to 0xffff if there's an underflow,\r
+ | | | 0x0 otherwise\r
+ 2 | 0x04 | MUL b, a | sets b to b*a, sets EX to ((b*a)>>16)&0xffff (treats b,\r
+ | | | a as unsigned)\r
+ 2 | 0x05 | MLI b, a | like MUL, but treat b, a as signed\r
+ 3 | 0x06 | DIV b, a | sets b to b/a, sets EX to ((b<<16)/a)&0xffff. if a==0,\r
+ | | | sets b and EX to 0 instead. (treats b, a as unsigned)\r
+ 3 | 0x07 | DVI b, a | like DIV, but treat b, a as signed. Rounds towards 0\r
+ 3 | 0x08 | MOD b, a | sets b to b%a. if a==0, sets b to 0 instead.\r
+ 3 | 0x09 | MDI b, a | like MOD, but treat b, a as signed. (MDI -7, 16 == -7)\r
+ 1 | 0x0a | AND b, a | sets b to b&a\r
+ 1 | 0x0b | BOR b, a | sets b to b|a\r
+ 1 | 0x0c | XOR b, a | sets b to b^a\r
+ 1 | 0x0d | SHR b, a | sets b to b>>>a, sets EX to ((b<<16)>>a)&0xffff \r
+ | | | (logical shift)\r
+ 1 | 0x0e | ASR b, a | sets b to b>>a, sets EX to ((b<<16)>>>a)&0xffff \r
+ | | | (arithmetic shift) (treats b as signed)\r
+ 1 | 0x0f | SHL b, a | sets b to b<<a, sets EX to ((b<<a)>>16)&0xffff\r
+\r
+ 2+| 0x10 | IFB b, a | performs next instruction only if (b&a)!=0\r
+ 2+| 0x11 | IFC b, a | performs next instruction only if (b&a)==0\r
+ 2+| 0x12 | IFE b, a | performs next instruction only if b==a \r
+ 2+| 0x13 | IFN b, a | performs next instruction only if b!=a \r
+ 2+| 0x14 | IFG b, a | performs next instruction only if b>a \r
+ 2+| 0x15 | IFA b, a | performs next instruction only if b>a (signed)\r
+ 2+| 0x16 | IFL b, a | performs next instruction only if b<a \r
+ 2+| 0x17 | IFU b, a | performs next instruction only if b<a (signed)\r
+ - | 0x18 | - |\r
+ - | 0x19 | - |\r
+ 3 | 0x1a | ADX b, a | sets b to b+a+EX, sets EX to 0x0001 if there is an over-\r
+ | | | flow, 0x0 otherwise\r
+ 3 | 0x1b | SBX b, a | sets b to b-a+EX, sets EX to 0xFFFF if there is an under-\r
+ | | | flow, 0x0 otherwise\r
+ - | 0x1c | - | \r
+ - | 0x1d | - |\r
+ 2 | 0x1e | STI b, a | sets b to a, then increases I and J by 1\r
+ 2 | 0x1f | STD b, a | sets b to a, then decreases I and J by 1\r
+---+------+----------+----------------------------------------------------------\r
+\r
+* The branching opcodes take one cycle longer to perform if the test fails\r
+ When they skip an if instruction, they will skip an additional instruction\r
+ at the cost of one extra cycle. This lets you easily chain conditionals. \r
+* Signed numbers are represented using two's complement.\r