X-Git-Url: http://git.squeep.com/?p=dcpu16;a=blobdiff_plain;f=dcpu16.c;h=0b1d391e58261f46332fa914aeda4673abe889df;hp=75c6cf0df39c3d0d33ce0bd06cf6bad984dd17b2;hb=HEAD;hpb=b819e4d8f696703ad42c97b357672fd9325bdac6 diff --git a/dcpu16.c b/dcpu16.c index 75c6cf0..0b1d391 100644 --- a/dcpu16.c +++ b/dcpu16.c @@ -11,6 +11,7 @@ /* * emulates the DCPU16 system from http://0x10c.com/doc/dcpu-16.txt + * currently emulates '1.7' spec from http://pastebin.com/Q4JvQvnM * * I couldn't remember ever implementing an emulator before, so this * happened. As such, consider this a toy in progress. @@ -18,10 +19,6 @@ * * Justin Wind * 2012 04 05 - implementation started - * 2012 04 06 - first functionality achieved - * 2012 04 09 - minor cleanups - * 2012 04 10 - moved cli to separate module - * 2012 04 12 - added basic callback support for address accesses * 2012 05 05 - start of v1.7 revisions * 2012 05 08 - v1.7 revisions mostly complete * @@ -30,7 +27,6 @@ * !! v1.7 hardware interface needs to be finished * !! v1.7 interrupts need to be finished * change api to print into buffers rather than stdio - * refactor opcode functiontables into switch statements * let callbacks determine whether to override events, or just observe * sort init callbacks by base addr, to call in-order * make all callbacks register addr range of interest @@ -42,55 +38,78 @@ static const char * const src_id_ = "$Id$"; #define OPCODE_OPERAND_B_BITS 5 #define OPCODE_OPERAND_A_BITS 6 -static const char * const regnames_ = "ABCXYZIJ"; +const char * const dcpu16_reg_names[] = { + "A", + "B", + "C", + "X", + "Y", + "Z", + "I", + "J", + "PC", + "SP", + "EX", + "IA", + NULL +}; -/* some default warning and debug reporting functions, which can be overridden by clients */ -#define WARN(...) do { if (warn_cb_) warn_cb_(__VA_ARGS__); } while (0) -static inline void warn_(char *fmt, ...) __attribute__((format(printf, 1, 2))); -static inline -void warn_(char *fmt, ...) { - va_list ap; +#define MSG_(__level__, __vm__, ...) do { ((__vm__) ? ((struct dcpu16 *)(__vm__))->msg_cb_ : dcpu16_msg_)((__level__), __VA_ARGS__); } while (0) +#define MSG_INFO(__vm__,...) MSG_(DCPU16_MSG_INFO, __vm__, __VA_ARGS__) +#define MSG_ERROR(__vm__,...) MSG_(DCPU16_MSG_ERROR, __vm__, __VA_ARGS__) +#ifdef DEBUG +#define MSG_DEBUG(__vm__,...) MSG_(DCPU16_MSG_DEBUG, __vm__, __VA_ARGS__) +#else /* DEBUG */ +#define MSG_DEBUG(__vm__,...) do {} while (0) +#endif /* DEBUG */ +#ifdef DEBUG_DECODE +#define MSG_DEBUG_DECODE (DCPU16_MSG_DEBUG + 2) +#endif /* DEBUG_DECODE - fprintf(stderr, "[warning] "); - va_start(ap, fmt); - vfprintf(stderr, fmt, ap); - va_end(ap); - fprintf(stderr, "\n"); - fflush(stderr); -} -static void (*warn_cb_)(char *fmt, ...) = warn_; -void dcpu16_warn_cb_set(void (*fn)(char *fmt, ...)) { - warn_cb_ = fn; -} +/* messages could be sent nowhere */ +static void msg_null_(unsigned int l, char *fmt, ...) { (void)l, (void)fmt; } -#ifdef DEBUG -#define TRACE(...) do { if (trace_cb_) trace_cb_(__VA_ARGS__); } while (0) -static inline void trace_(char *fmt, ...) __attribute__((format(printf, 1, 2))); +/* messages default to standard streams */ +static void msg_default_(unsigned int, char *, ...) __attribute__((format(printf, 2, 3))); static inline -void trace_(char *fmt, ...) { +void msg_default_(unsigned int l, char *fmt, ...) { + static const char * const msg_tag_[] = { "info", "error", "debug" }; + FILE *f = (l <= DCPU16_MSG_INFO) ? stderr : stdout; va_list ap; - fprintf(stdout, "[debug] "); + if (l < sizeof msg_tag_ / sizeof *msg_tag_) + fprintf(f, "[%s] ", msg_tag_[l]); + else + fprintf(f, "[%u] ", l); + va_start(ap, fmt); - vfprintf(stdout, fmt, ap); + vfprintf(f, fmt, ap); va_end(ap); - fprintf(stdout, "\n"); - fflush(stdout); -} -#else /* DEBUG */ -#define TRACE(...) do {} while(0) -#endif /* DEBUG */ -static void (*trace_cb_)(char *fmt, ...) = -#ifdef DEBUG - trace_ -#else /* DEBUG */ - NULL -#endif - ; -void dcpu16_trace_cb_set(void (*fn)(char *fmt, ...)) { - trace_cb_ = fn; + + fprintf(f, "\n"); + + fflush(f); } +/* dcpu16 message callback + * This function pointer is copied into newly instantiated dcpu16 structures, + * and is invoked directly for messages independant of a dcpu16 context. + */ +dcpu16_msg_cb_t *dcpu16_msg_ = msg_default_; + +/* set a new default message callback */ +/* returns the previous setting */ +dcpu16_msg_cb_t *dcpu16_msg_set_default(dcpu16_msg_cb_t *msg_cb) { + dcpu16_msg_cb_t *r = dcpu16_msg_; + dcpu16_msg_ = msg_cb ? msg_cb : msg_null_; + return r; +} +/* set a new callback */ +dcpu16_msg_cb_t *dcpu16_msg_set(struct dcpu16 *vm, dcpu16_msg_cb_t *msg_cb) { + dcpu16_msg_cb_t *r = vm->msg_cb_; + vm->msg_cb_ = msg_cb ? msg_cb : msg_null_; + return r; +} /* acct_event_ * invokes callbacks for specified event @@ -102,26 +121,22 @@ void acct_event_(struct dcpu16 *vm, dcpu16_acct_event ev, DCPU16_WORD addr) { for (i = 0; i < vm->cb_table_entries_; i++) { if ( (cb[i].mask & ev) ) - cb[i].fn(vm, ev, addr, cb[i].data); + if (addr >= cb[i].addr_l && addr <= cb[i].addr_h) + cb[i].fn(vm, ev, addr, cb[i].data); } } -/* convert register name to index into register array */ -static inline -off_t reg_index_(int reg) { - return strchr(regnames_, reg) - regnames_; -} /* add an entry to the interrupt queue */ static -int interrupt_enqueue_(struct dcpu16 *d, DCPU16_WORD message) { - d->interrupts_[d->interrupts_tail_] = message; - d->interrupts_tail_ += 1; - d->interrupts_tail_ %= DCPU16_INTERRUPT_QUEUE_SIZE; - - if (d->interrupts_tail_ == d->interrupts_head_) { - d->on_fire_ = 1; - WARN("interrupt queue overflow (system is now on fire)"); +int interrupt_enqueue_(struct dcpu16 *vm, DCPU16_WORD message) { + vm->interrupts_[vm->interrupts_tail_] = message; + vm->interrupts_tail_ += 1; + vm->interrupts_tail_ %= DCPU16_INTERRUPT_QUEUE_SIZE; + + if (vm->interrupts_tail_ == vm->interrupts_head_) { + vm->on_fire_ = 1; + MSG_INFO(vm, "interrupt queue overflow (system is now on fire)"); return -1; } @@ -129,21 +144,42 @@ int interrupt_enqueue_(struct dcpu16 *d, DCPU16_WORD message) { } static -DCPU16_WORD interrupt_dequeue_(struct dcpu16 *d) { +DCPU16_WORD interrupt_dequeue_(struct dcpu16 *vm) { DCPU16_WORD message; - if (d->interrupts_tail_ == d->interrupts_head_) { - WARN("interrupt underflow"); + if (vm->interrupts_tail_ == vm->interrupts_head_) { + MSG_INFO(vm, "interrupt underflow"); return 0; } - message = d->interrupts_[d->interrupts_head_]; - d->interrupts_head_ += 1; - d->interrupts_head_ %= DCPU16_INTERRUPT_QUEUE_SIZE; + message = vm->interrupts_[vm->interrupts_head_]; + vm->interrupts_head_ += 1; + vm->interrupts_head_ %= DCPU16_INTERRUPT_QUEUE_SIZE; return message; } +inline +void dcpu16_cycle_inc(struct dcpu16 *vm, unsigned int n) { + size_t i; + + while (n--) { + /* new cycle */ + vm->cycle_ += 1; + MSG_DEBUG(vm, "%s>> starting cycle %llu", __func__, vm->cycle_); + + /* signal interested cycle hooks */ + acct_event_(vm, DCPU16_ACCT_EV_CYCLE, vm->reg[DCPU16_REG_PC]); + + /* signal attached hardware */ + for (i = 0; i < vm->hw_table_entries_; i++) { + MSG_DEBUG(vm, "%s>> notifying %s", __func__, vm->hw_table_[i].mod->name_); + if (vm->hw_table_[i].mod->cycle) + vm->hw_table_[i].mod->cycle(vm, &vm->hw_table_[i]); + } + } +} + /* value_decode_ * sets *v to be the address of the represented value * value_is_a is 0 for b, 1 for a, alters behavior of some operands @@ -152,148 +188,225 @@ DCPU16_WORD interrupt_dequeue_(struct dcpu16 *d) { * e_addr is set to a referenced address, for accounting callback * pc_adjust is set to how to change the program counter * stack_adjust is set to how to change the stack pointer - * cycles is set to number of cycles spent looking up operand + * cycle_adjust is set to number of cycles spent looking up operand * * zero all adjustables before decoding first operand, and pass in these values when * decoding next operand.. * */ +#define EWHAT_NONE (0) +#define EWHAT_REG (1<<1) +#define EWHAT_RAM (1<<2) static inline -void value_decode_(struct dcpu16 *d, DCPU16_WORD value, unsigned int value_is_a, DCPU16_WORD value_data, - DCPU16_WORD *work_v, DCPU16_WORD **v, DCPU16_WORD *e_addr, +void value_decode_(struct dcpu16 *vm, DCPU16_WORD value, unsigned int value_is_a, DCPU16_WORD value_data, + DCPU16_WORD *work_v, DCPU16_WORD **v, DCPU16_WORD *e_addr, enum dcpu16_register_indexes *e_reg, unsigned int *e_what, short *pc_adjust, short *sp_adjust, unsigned int *cycle_adjust) { assert(value <= 0x3f); - DCPU16_WORD pc = (DCPU16_WORD)(d->pc + *pc_adjust), - sp = (DCPU16_WORD)(d->sp + *sp_adjust); + DCPU16_WORD pc = (DCPU16_WORD)(vm->reg[DCPU16_REG_PC] + *pc_adjust), + sp = (DCPU16_WORD)(vm->reg[DCPU16_REG_SP] + *sp_adjust); - TRACE("%s: pc:0x%04x sp:0x%04x value_data:0x%04x\n", - __func__, - pc, - sp, - value_data); + (void)pc; + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm ,"%s>> is_a:%u pc:0x%04x sp:0x%04x value_data:0x%04x\n", + __func__, + value_is_a, + pc, + sp, + value_data); +#endif /* DEBUG_DECODE */ if (value <= 0x07) { /* register */ - *v = d->reg + value; - TRACE("%s>> %c (0x%04x)", + *e_what = EWHAT_REG; + *e_reg = value & 0x07; + *v = vm->reg + *e_reg; + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> %s (0x%04x)", __func__, - regnames_[value], + dcpu16_reg_names[value], **v); +#endif /* DEBUG_DECODE */ + return; } if (value <= 0x0f) { /* [register] */ - *v = &(d->ram[ d->reg[value & 0x07] ]); - *e_addr = d->reg[value & 0x07]; - TRACE("%s>> [%c] [0x%04x] (0x%04x)", + *e_what = EWHAT_RAM; + *e_addr = vm->reg[value & 0x07]; + *v = &(vm->ram[ *e_addr ]); + acct_event_(vm, DCPU16_ACCT_EV_REG_READ, value & 0x07); + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> [%s] [0x%04x] (0x%04x)", __func__, - regnames_[value & 0x07], - d->reg[value & 0x07], + dcpu16_reg_names[value & 0x07], + vm->reg[value & 0x07], **v); +#endif /* DEBUG_DECODE */ + return; } if (value <= 0x17) { /* [next word + register] */ + acct_event_(vm, DCPU16_ACCT_EV_REG_WRITE, DCPU16_REG_PC); *pc_adjust += 1; /* consume next word */ *cycle_adjust += 1; - *e_addr = value_data + d->reg[value & 0x07]; - *v = d->ram + *e_addr; - TRACE("%s>> [nextword + %c] [0x%04x + 0x%04x] (0x%04x)", + *e_what = EWHAT_RAM; + *e_addr = value_data + vm->reg[value & 0x07]; + acct_event_(vm, DCPU16_ACCT_EV_REG_READ, value & 0x07); + *v = vm->ram + *e_addr; + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> [nextword + %s] [0x%04x + 0x%04x] (0x%04x)", __func__, - regnames_[value & 0x07], + dcpu16_reg_names[value & 0x07], value_data, - d->reg[value & 0x07], + vm->reg[value & 0x07], **v); +#endif /* DEBUG_DECODE */ + return; } switch (value) { case 0x18: /* PUSH/[--SP] or POP/[SP++] */ + *e_what = EWHAT_RAM; + acct_event_(vm, DCPU16_ACCT_EV_REG_READ, DCPU16_REG_SP); + acct_event_(vm, DCPU16_ACCT_EV_REG_WRITE, DCPU16_REG_SP); if (value_is_a == 0) { /* b */ - *v = &(d->ram[sp - 1]); + *v = &(vm->ram[sp - 1]); *sp_adjust -= 1; *e_addr = sp - 1; - TRACE("%s>> PUSH [0x%04x] (0x%04x)", __func__, sp - 1, **v); + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> PUSH [0x%04x] (0x%04x)", __func__, sp - 1, **v); +#endif /* DEBUG_DECODE */ + } else { /* a */ - *v = &(d->ram[sp]); + *v = &(vm->ram[sp]); *sp_adjust += 1; *e_addr = sp; - TRACE("%s>> POP [0x%04x] (0x%04x)", __func__, sp, **v); + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> POP [0x%04x] (0x%04x)", __func__, sp, **v); +#endif /* DEBUG_DECODE */ + } break; case 0x19: /* PEEK/[SP] */ - *v = &(d->ram[sp]); + acct_event_(vm, DCPU16_ACCT_EV_REG_READ, DCPU16_REG_SP); + *e_what = EWHAT_RAM; + *v = &(vm->ram[sp]); *e_addr = sp; - TRACE("%s>> PEEK [0x%04x] (0x%04x)", + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> PEEK [0x%04x] (0x%04x)", __func__, sp, **v); +#endif /* DEBUG_DECODE */ break; case 0x1a: /* PICK n */ + acct_event_(vm, DCPU16_ACCT_EV_REG_READ, DCPU16_REG_SP); + *e_what = EWHAT_RAM; *pc_adjust += 1; *cycle_adjust += 1; *e_addr = sp + value_data; - *v = d->ram + *e_addr; - TRACE("%s>> PICK 0x%04x [0x%04x] (0x%04x)", + *v = vm->ram + *e_addr; + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> PICK 0x%04x [0x%04x] (0x%04x)", __func__, value_data, sp + value_data, **v); +#endif /* DEBUG_DECODE */ break; case 0x1b: /* SP */ - *v = &(d->sp); - TRACE("%s>> %s (0x%04x)", + *e_reg = DCPU16_REG_SP; + *e_what = EWHAT_REG; + *v = &(vm->reg[DCPU16_REG_SP]); + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> %s (0x%04x)", __func__, - "SP", + dcpu16_reg_names[DCPU16_REG_SP], **v); +#endif /* DEBUG_DECODE */ break; case 0x1c: /* PC */ - *v = &(d->pc); - TRACE("%s>> %s (0x%04x)", + *e_reg = DCPU16_REG_PC; + *e_what = EWHAT_REG; + *v = &(vm->reg[DCPU16_REG_PC]); + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> %s (0x%04x)", __func__, - "PC", + dcpu16_reg_names[DCPU16_REG_PC], **v); +#endif /* DEBUG_DECODE */ break; case 0x1d: /* EX */ - *v = &(d->ex); - TRACE("%s>> %s (0x%04x)", + *e_reg = DCPU16_REG_EX; + *e_what = EWHAT_REG; + *v = &(vm->reg[DCPU16_REG_EX]); + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> %s (0x%04x)", __func__, - "EX", + dcpu16_reg_names[DCPU16_REG_EX], **v); +#endif /* DEBUG_DECODE */ break; case 0x1e: /* [next word] / [[pc++]] */ + *e_what = EWHAT_RAM; + acct_event_(vm, DCPU16_ACCT_EV_REG_WRITE, DCPU16_REG_PC); *pc_adjust += 1; *cycle_adjust += 1; *e_addr = value_data; - *v = d->ram + *e_addr; - TRACE("%s>> [nextword] [0x%04x] (0x%04x)", + *v = vm->ram + *e_addr; + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> [nextword] [0x%04x] (0x%04x)", __func__, value_data, **v); +#endif /* DEBUG_DECODE */ break; case 0x1f: /* next word (literal) / [pc++] */ + *e_what = EWHAT_NONE; + acct_event_(vm, DCPU16_ACCT_EV_REG_WRITE, DCPU16_REG_PC); *pc_adjust += 1; *cycle_adjust += 1; *work_v = value_data; *v = work_v; - TRACE("%s>> nextword (0x%04x)", + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> nextword (0x%04x)", __func__, **v); +#endif /* DEBUG_DECODE */ break; default: /* 0x20-0x3f: literal values 0xffff-0x1e */ + *e_what = EWHAT_NONE; *work_v = (value & 0x1f) - 1; *v = work_v; - TRACE("%s>> literal (0x%04x)", + +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, vm, "%s>> literal (0x%04x)", __func__, **v); +#endif /* DEBUG_DECODE */ } } @@ -310,23 +423,25 @@ struct opcode_entry { /* opcode doesn't adjust its own PC, the step function which invoked it handles that */ /* opcode does adjust stack and cycle count */ -#define OP_IMPL(x) static void op_##x(struct dcpu16 *d, DCPU16_WORD val_b, DCPU16_WORD val_b_data, DCPU16_WORD val_a, DCPU16_WORD val_a_data) +#define OP_IMPL(x) static void op_##x(struct dcpu16 *vm, DCPU16_WORD val_b, DCPU16_WORD val_b_data, DCPU16_WORD val_a, DCPU16_WORD val_a_data) #define OP_TYPE(op_type) DCPU16_WORD *a, *b;\ DCPU16_WORD ev_a_addr = 0, ev_b_addr = 0;\ + enum dcpu16_register_indexes ev_a_reg = DCPU16_REG__NUM, ev_b_reg = DCPU16_REG__NUM;\ + unsigned int ev_a_what = 0, ev_b_what = 0;\ short pc_adjust = 0, sp_adjust = 0;\ unsigned int cycle_adjust = 0;\ do {\ op_type;\ - value_decode_(d, val_a, 1, val_a_data,\ - &d->reg_work_[1], &a, &ev_a_addr,\ + value_decode_(vm, val_a, 1, val_a_data,\ + &vm->reg_work_[1], &a, &ev_a_addr, &ev_a_reg, &ev_a_what,\ &pc_adjust, &sp_adjust, &cycle_adjust);\ - d->sp += sp_adjust;\ - d->cycle += cycle_adjust;\ + vm->reg[DCPU16_REG_SP] += sp_adjust;\ + if (cycle_adjust) dcpu16_cycle_inc(vm, cycle_adjust);\ } while (0) -#define OP_NBI_ (void)val_b, (void)b, (void)ev_b_addr, (void)val_b_data -#define OP_BASIC_ value_decode_(d, val_b, 0, val_b_data,\ - &d->reg_work_[0], &b, &ev_b_addr,\ +#define OP_NBI_ (void)val_b, (void)b, (void)ev_b_addr, (void)val_b_data, (void)ev_b_reg, (void)ev_b_what +#define OP_BASIC_ value_decode_(vm, val_b, 0, val_b_data,\ + &vm->reg_work_[0], &b, &ev_b_addr, &ev_b_reg, &ev_b_what,\ &pc_adjust, &sp_adjust, &cycle_adjust) #define OP_BASIC(x) OP_TYPE(OP_BASIC_) #define OP_NBI(x) OP_TYPE(OP_NBI_) @@ -337,9 +452,20 @@ struct opcode_entry { accounting helpers, these fire off the related callbacks for memory reads, memory writes, and execution of reserved instructions */ -#define ACCT_R(addr) do { acct_event_(d, DCPU16_ACCT_EV_READ, addr); } while (0) -#define ACCT_W(addr) do { acct_event_(d, DCPU16_ACCT_EV_WRITE, addr); } while (0) -#define ACCT_ILL(addr) do { acct_event_(d, DCPU16_ACCT_EV_NOP, addr); } while (0) +#define ACCT_ILL(addr) do { acct_event_(vm, DCPU16_ACCT_EV_NOP, addr); } while (0) +#define ACCT_RAM_R(addr) do { acct_event_(vm, DCPU16_ACCT_EV_READ, addr); } while (0) +#define ACCT_RAM_W(addr) do { acct_event_(vm, DCPU16_ACCT_EV_WRITE, addr); } while (0) +#define ACCT_REG_R(reg) do { acct_event_(vm, DCPU16_ACCT_EV_REG_READ, reg); } while (0) +#define ACCT_REG_W(reg) do { acct_event_(vm, DCPU16_ACCT_EV_REG_WRITE, reg); } while (0) + +#define ACCT_R(__x__) do {\ + if (ev_##__x__##_what & EWHAT_REG) ACCT_REG_R(ev_##__x__##_reg);\ + if (ev_##__x__##_what & EWHAT_RAM) ACCT_RAM_R(ev_##__x__##_addr);\ +} while (0) +#define ACCT_W(__x__) do {\ + if (ev_##__x__##_what & EWHAT_REG) ACCT_REG_W(ev_##__x__##_reg);\ + if (ev_##__x__##_what & EWHAT_RAM) ACCT_RAM_W(ev_##__x__##_addr);\ +} while (0) /* extended opcodes */ @@ -355,153 +481,210 @@ OP_IMPL(nbi__reserved_) { /* reserved for future expansion */ /* fire an illegal instruction event for current instruction */ - DCPU16_WORD future_opcode = (d->ram[d->pc - pc_adjust] >> (OPCODE_BASIC_BITS + OPCODE_OPERAND_B_BITS)); - WARN("reserved future opcode 0x%04x invoked", future_opcode); + DCPU16_WORD future_opcode = (vm->ram[vm->reg[DCPU16_REG_PC] - pc_adjust] >> (OPCODE_BASIC_BITS + OPCODE_OPERAND_B_BITS)); + + MSG_INFO(vm, "reserved future opcode 0x%04x invoked", future_opcode); + + ACCT_ILL(vm->reg[DCPU16_REG_PC] - pc_adjust); - ACCT_ILL(d->pc - pc_adjust); + dcpu16_cycle_inc(vm, 1); } OP_IMPL(nbi_jsr) { OP_NBI(nbi_jsr); /* pushes the address of the next instruction to the stack, then sets PC to a */ - ACCT_R(ev_a_addr); + ACCT_R(a); - d->ram[ --d->sp ] = d->pc; - d->pc = *a; + ACCT_REG_R(DCPU16_REG_PC); + ACCT_REG_R(DCPU16_REG_SP); + vm->ram[ --vm->reg[DCPU16_REG_SP] ] = vm->reg[DCPU16_REG_PC]; + ACCT_REG_W(DCPU16_REG_SP); + ACCT_RAM_W(vm->reg[DCPU16_REG_SP] + 1); - d->cycle += 2; + vm->reg[DCPU16_REG_PC] = *a; + ACCT_REG_W(DCPU16_REG_PC); - ACCT_W(d->sp + 1); + + dcpu16_cycle_inc(vm, 2); } OP_IMPL(nbi__reserved2_) { OP_NBI(nbi__reserved2_); /* reserved */ - WARN("reserved nbi opcode invoked"); + MSG_INFO(vm, "reserved nbi opcode invoked"); + + ACCT_ILL(vm->reg[DCPU16_REG_PC] - pc_adjust); - ACCT_ILL(d->pc - pc_adjust); + dcpu16_cycle_inc(vm, 1); } OP_IMPL(nbi_int) { OP_NBI(nbi_int); - ACCT_R(ev_a_addr); + ACCT_R(a); - if (d->ia) { - if ( interrupt_enqueue_(d, *a) ) { - WARN("failed to queue interrupt"); + ACCT_REG_R(DCPU16_REG_IA); + if (vm->reg[DCPU16_REG_IA]) { + if ( interrupt_enqueue_(vm, *a) ) { + MSG_INFO(vm, "failed to queue interrupt"); return; } - if (d->interrupts_deferred_) + if (vm->interrupts_deferred_) return; - d->interrupts_deferred_ = 1; - d->ram[--d->sp] = d->pc; - d->ram[--d->sp] = d->reg[reg_index_('A')]; - d->pc = d->ia; - d->reg[0] = *a; + vm->interrupts_deferred_ = 1; + + ACCT_REG_R(DCPU16_REG_PC); + ACCT_REG_R(DCPU16_REG_SP); + vm->ram[--vm->reg[DCPU16_REG_SP]] = vm->reg[DCPU16_REG_PC]; + ACCT_RAM_W(vm->reg[DCPU16_REG_SP] + 1); + ACCT_REG_W(DCPU16_REG_SP); + + ACCT_REG_R(DCPU16_REG_A); + ACCT_REG_R(DCPU16_REG_SP); + vm->ram[--vm->reg[DCPU16_REG_SP]] = vm->reg[DCPU16_REG_A]; + ACCT_RAM_W(vm->reg[DCPU16_REG_SP] + 1); + ACCT_REG_W(DCPU16_REG_SP); + + ACCT_REG_R(DCPU16_REG_IA); + vm->reg[DCPU16_REG_PC] = vm->reg[DCPU16_REG_IA]; + ACCT_REG_W(DCPU16_REG_PC); + + vm->reg[DCPU16_REG_A] = *a; + ACCT_REG_W(DCPU16_REG_A); } - d->cycle += 4; + dcpu16_cycle_inc(vm, 4); } OP_IMPL(nbi_iag) { OP_NBI(nbi_iag); - *a = d->ia; + ACCT_REG_R(DCPU16_REG_IA); + *a = vm->reg[DCPU16_REG_IA]; + + ACCT_W(a); - ACCT_W(ev_a_addr); + dcpu16_cycle_inc(vm, 1); } OP_IMPL(nbi_ias) { OP_NBI(nbi_ias); - d->ia = *a; + ACCT_R(a); + + vm->reg[DCPU16_REG_IA] = *a; + ACCT_REG_W(DCPU16_REG_IA); - ACCT_R(ev_a_addr); + dcpu16_cycle_inc(vm, 1); } /* does this just ignore its operand? */ OP_IMPL(nbi_rfi) { OP_NBI(nbi_rfi); - d->interrupts_deferred_ = 0; - d->reg[reg_index_('A')] = d->ram[d->sp++]; - d->pc = d->ram[d->sp++]; + /* well, it consumes the argument, currently, so I guess pretend like we care */ + ACCT_R(a); + + vm->interrupts_deferred_ = 0; + + ACCT_REG_R(DCPU16_REG_SP); + ACCT_RAM_R(vm->reg[DCPU16_REG_SP]); + vm->reg[DCPU16_REG_A] = vm->ram[vm->reg[DCPU16_REG_SP]++]; + ACCT_REG_W(DCPU16_REG_A); + ACCT_REG_W(DCPU16_REG_SP); + + ACCT_REG_R(DCPU16_REG_SP); + ACCT_RAM_R(vm->reg[DCPU16_REG_SP]); + vm->reg[DCPU16_REG_PC] = vm->ram[vm->reg[DCPU16_REG_SP]++]; + ACCT_REG_W(DCPU16_REG_PC); + ACCT_REG_W(DCPU16_REG_SP); + + dcpu16_cycle_inc(vm, 3); } OP_IMPL(nbi_iaq) { OP_NBI(nbi_iaq); + ACCT_R(a); + if (*a) { - d->interrupts_deferred_ = 1; + vm->interrupts_deferred_ = 1; } else { - d->interrupts_deferred_ = 0; + vm->interrupts_deferred_ = 0; } - ACCT_R(ev_a_addr); + dcpu16_cycle_inc(vm, 2); } OP_IMPL(nbi_hwn) { OP_NBI(nbi_hwn); - ACCT_W(ev_a_addr); + *a = vm->hw_table_entries_; + ACCT_W(a); - *a = d->hw_table_entries_; - - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(nbi_hwq) { OP_NBI(nbi_hwq); - ACCT_R(ev_a_addr); + ACCT_R(a); - if (*a >= d->hw_table_entries_) { - WARN("hardware query for non-extant device 0x%04x", *a); - d->reg[reg_index_('A')] = 0; - d->reg[reg_index_('B')] = 0; - d->reg[reg_index_('C')] = 0; - d->reg[reg_index_('X')] = 0; - d->reg[reg_index_('Y')] = 0; - return; + if (*a >= vm->hw_table_entries_) { + MSG_INFO(vm, "hardware query for non-extant device 0x%04x", *a); + vm->reg[DCPU16_REG_A] = 0; + vm->reg[DCPU16_REG_B] = 0; + vm->reg[DCPU16_REG_C] = 0; + vm->reg[DCPU16_REG_X] = 0; + vm->reg[DCPU16_REG_Y] = 0; + } else { + vm->reg[DCPU16_REG_A] = vm->hw_table_[*a].mod->id_l; + vm->reg[DCPU16_REG_B] = vm->hw_table_[*a].mod->id_h; + vm->reg[DCPU16_REG_C] = vm->hw_table_[*a].mod->ver; + vm->reg[DCPU16_REG_X] = vm->hw_table_[*a].mod->mfg_l; + vm->reg[DCPU16_REG_Y] = vm->hw_table_[*a].mod->mfg_h; } - d->reg[reg_index_('A')] = d->hw_table_[*a].id_l; - d->reg[reg_index_('B')] = d->hw_table_[*a].id_h; - d->reg[reg_index_('C')] = d->hw_table_[*a].ver; - d->reg[reg_index_('X')] = d->hw_table_[*a].mfg_l; - d->reg[reg_index_('Y')] = d->hw_table_[*a].mfg_h; + ACCT_REG_W(DCPU16_REG_A); + ACCT_REG_W(DCPU16_REG_B); + ACCT_REG_W(DCPU16_REG_C); + ACCT_REG_W(DCPU16_REG_X); + ACCT_REG_W(DCPU16_REG_Y); - d->cycle += 4; + dcpu16_cycle_inc(vm, 4); } OP_IMPL(nbi_hwi) { OP_NBI(nbi_hwi); - ACCT_R(ev_a_addr); + ACCT_R(a); - if (*a > d->hw_table_entries_) { - WARN("interrupt for non-extant device 0x%04x", *a); + if (*a > vm->hw_table_entries_) { + MSG_INFO(vm, "interrupt for non-extant device 0x%04x", *a); return; } - d->cycle += 4; - d->hw_table_[*a].int_fn(d, d->hw_table_[*a].data); + if (vm->hw_table_[*a].mod->hwi) + vm->hw_table_[*a].mod->hwi(vm, &vm->hw_table_[*a]); + else + MSG_INFO(vm, "hardware 0x%04x has no interrupt handler", *a); + + dcpu16_cycle_inc(vm, 4); } OP_IMPL(nbi_hcf) { OP_NBI(nbi_hcf); - ACCT_R(ev_a_addr); + ACCT_R(a); - d->on_fire_ = 1; - WARN("system on fire"); + vm->on_fire_ = 1; + MSG_INFO(vm, "system on fire"); - d->cycle += 9; + dcpu16_cycle_inc(vm, 9); } static const struct opcode_entry opcode_nbi_entries[] = { @@ -533,7 +716,7 @@ static const struct opcode_entry opcode_nbi_entries[] = { /* basic opcodes */ /* - N.B. the following function does not decode values, (thus does not advance sp) + N.B. the following function does not decode values. Decoding is handled by the secondary opcode functions it calls. */ OP_IMPL(_nbi_) { @@ -550,15 +733,15 @@ OP_IMPL(_nbi_) { assert(e->impl != NULL); - TRACE(">> %s 0x%04x", e->name, val_b); - e->impl(d, 0, 0, val_a, val_a_data); + MSG_DEBUG(vm, "%s>> %s 0x%04x", __func__, e->name, val_b); + e->impl(vm, 0, 0, val_a, val_a_data); } OP_IMPL(set) { OP_BASIC(set); /* sets b to a */ - ACCT_R(ev_a_addr); + ACCT_R(a); /* if b is a literal, it's aimed at a scratch register, @@ -566,9 +749,9 @@ OP_IMPL(set) { */ *b = *a; - d->cycle += 1; + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 1); } OP_IMPL(add) { @@ -576,15 +759,17 @@ OP_IMPL(add) { /* sets b to b+a, sets EX to 0x0001 if there's an overflow, 0x0 otherwise */ unsigned int acc = *b + *a; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = acc; - d->ex = (acc > 0xffff); + vm->reg[DCPU16_REG_EX] = (acc > 0xffff); - d->cycle += 2; + ACCT_REG_W(DCPU16_REG_EX); - ACCT_W(ev_b_addr); + ACCT_W(b); + + dcpu16_cycle_inc(vm, 2); } OP_IMPL(sub) { @@ -592,15 +777,17 @@ OP_IMPL(sub) { /* sets b to b-a, sets EX to 0xffff if there's an underflow, 0x0 otherwise */ unsigned int acc = *b - *a; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = acc; - d->ex = (acc > 0xffff); + vm->reg[DCPU16_REG_EX] = (acc > 0xffff); + + ACCT_REG_W(DCPU16_REG_EX); - d->cycle += 2; + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 2); } OP_IMPL(mul) { @@ -608,15 +795,17 @@ OP_IMPL(mul) { /* sets b to b*a, unsigned, sets EX to ((b*a)>>16)&0xffff */ unsigned int acc = *b * *a; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = acc; - d->ex = acc >> 16; + vm->reg[DCPU16_REG_EX] = acc >> 16; - d->cycle += 2; + ACCT_REG_W(DCPU16_REG_EX); - ACCT_W(ev_b_addr); + ACCT_W(b); + + dcpu16_cycle_inc(vm, 2); } OP_IMPL(mli) { @@ -624,63 +813,68 @@ OP_IMPL(mli) { /* sets b to b*a, signed */ int acc = (short)*b * (short)*a; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = acc; - d->ex = acc >> 16; + vm->reg[DCPU16_REG_EX] = acc >> 16; + + ACCT_REG_W(DCPU16_REG_EX); - d->cycle += 2; + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 2); } OP_IMPL(div) { OP_BASIC(div); /* sets b to b/a, sets EX to ((b<<16)/a)&0xffff. if a==0, sets a and EX to 0 instead. */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if (*a == 0) { *b = 0; - d->ex = 0; + vm->reg[DCPU16_REG_EX] = 0; } else { *b = *b / *a; - d->ex = (*b << 16) / *a; + vm->reg[DCPU16_REG_EX] = (*b << 16) / *a; } - d->cycle += 3; + ACCT_REG_W(DCPU16_REG_EX); + + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 3); } OP_IMPL(dvi) { OP_BASIC(dvi); /* sets b to b/a, signed, round towards 0 */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if (*a == 0) { *b = 0; - d->ex = 0; + vm->reg[DCPU16_REG_EX] = 0; } else { *b = (short)*b / (short)*a; - d->ex = (short)(*b << 16) / (short)*a; + vm->reg[DCPU16_REG_EX] = (short)(*b << 16) / (short)*a; } - d->cycle += 3; + ACCT_REG_W(DCPU16_REG_EX); + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 3); } OP_IMPL(mod) { OP_BASIC(mod); /* sets b to b%a. if a==0, sets b to 0 instead. */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if (*a == 0) { *b = 0; @@ -688,17 +882,17 @@ OP_IMPL(mod) { *b = *b % *a; } - d->cycle += 3; + ACCT_W(a); - ACCT_W(ev_a_addr); + dcpu16_cycle_inc(vm, 3); } OP_IMPL(mdi) { OP_BASIC(mdi); /* sets b to b%a, signed */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if (*a == 0) { *b = 0; @@ -706,51 +900,51 @@ OP_IMPL(mdi) { *b = (short)*b % (short)*a; } - d->cycle += 3; + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 3); } OP_IMPL(and) { OP_BASIC(and); /* sets b to b&a */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = *b & *a; - d->cycle += 1; + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 1); } OP_IMPL(bor) { OP_BASIC(bor); /* sets b to b|a */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = *b | *a; - d->cycle += 1; + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 1); } OP_IMPL(xor) { OP_BASIC(xor); /* sets b to b^a */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = *b ^ *a; - d->cycle += 1; + dcpu16_cycle_inc(vm, 1); - ACCT_W(ev_b_addr); + ACCT_W(b); } OP_IMPL(shr) { @@ -758,17 +952,18 @@ OP_IMPL(shr) { /* sets b to b>>>a, sets EX to ((b<<16)>>a)&0xffff */ unsigned int acc = *b >> *a; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = acc & 0xffff; - d->ex = (*b << 16) >> *a; + vm->reg[DCPU16_REG_EX] = (*b << 16) >> *a; - d->cycle += 2; + MSG_ERROR(vm, "IMPLEMENT"); - WARN("IMPLEMENT"); + ACCT_REG_W(DCPU16_REG_EX); + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 2); } OP_IMPL(asr) { @@ -776,17 +971,18 @@ OP_IMPL(asr) { /* sets b to b>>a, sets EX to ((b<<16)>>>a)&0xffff (arithmetic shift) (treats b as signed) */ unsigned int acc = *b << *a; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = acc & 0xffff; - d->ex = (*b << 16) >> *a; + vm->reg[DCPU16_REG_EX] = (*b << 16) >> *a; - d->cycle += 2; + MSG_ERROR(vm, "IMPLEMENT"); - WARN("IMPLEMENT"); + ACCT_REG_W(DCPU16_REG_EX); + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 2); } OP_IMPL(shl) { @@ -794,152 +990,153 @@ OP_IMPL(shl) { /* sets b to b<>16)&0xffff */ unsigned int acc = *b << *a; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = acc; - d->ex = acc >> 16; + vm->reg[DCPU16_REG_EX] = acc >> 16; - d->cycle += 2; + ACCT_REG_W(DCPU16_REG_EX); + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 2); } OP_IMPL(ifb) { OP_BASIC(ifb); /* performs next instruction only if (b&a)!=0 */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if ((*b & *a) != 0) { /* */ } else { - d->skip_ = 1; - d->cycle += 1; + vm->skip_ = 1; + dcpu16_cycle_inc(vm, 1); } - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(ifc) { OP_BASIC(ifc); /* performs next instruction only if (b&a)==0 */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if ((*b & *a) == 0) { - + /* */ } else { - d->skip_ = 1; - d->cycle += 1; + vm->skip_ = 1; + dcpu16_cycle_inc(vm, 1); } - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(ife) { OP_BASIC(ife); /* performs next instruction only if b==a */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if (*b == *a) { /* */ } else { - d->skip_ = 1; - d->cycle += 1; + vm->skip_ = 1; + dcpu16_cycle_inc(vm, 1); } - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(ifn) { OP_BASIC(ifn); /* performs next instruction only if b!=a */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if (*b != *a) { /* */ } else { - d->skip_ = 1; - d->cycle++; + vm->skip_ = 1; + dcpu16_cycle_inc(vm, 1); } - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(ifg) { OP_BASIC(ifg); /* performs next instruction only if b>a */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if (*b > *a) { /* */ } else { - d->skip_ = 1; - d->cycle++; + vm->skip_ = 1; + dcpu16_cycle_inc(vm, 1); } - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(ifa) { OP_BASIC(ifa); /* performs next instruction only if b>a (signed) */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); if (*b > *a) { /* */ } else { - d->skip_ = 1; - d->cycle += 1; + vm->skip_ = 1; + dcpu16_cycle_inc(vm, 1); } - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(ifl) { OP_BASIC(ifl); /* performs next instruction only if bskip_ = 1; - d->cycle++; + vm->skip_ = 1; + dcpu16_cycle_inc(vm, 1); } - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(ifu) { OP_BASIC(ifu); /* performs next instruction only if bskip_ = 1; - d->cycle += 1; + vm->skip_ = 1; + dcpu16_cycle_inc(vm, 1); } - d->cycle += 2; + dcpu16_cycle_inc(vm, 2); } OP_IMPL(adx) { @@ -947,19 +1144,22 @@ OP_IMPL(adx) { /* sets b to b+a+EX, sets EX to 0x0001 if overflow, 0x0 otherwise */ unsigned int acc; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); + + ACCT_REG_R(DCPU16_REG_EX); - acc = *b + *a + d->ex; + acc = *b + *a + vm->reg[DCPU16_REG_EX]; *b = acc & 0xffff; if (acc > 0xffff) - d->ex = 0x0001; + vm->reg[DCPU16_REG_EX] = 0x0001; else - d->ex = 0x0000; + vm->reg[DCPU16_REG_EX] = 0x0000; - d->cycle += 3; + ACCT_REG_W(DCPU16_REG_EX); + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 3); } OP_IMPL(sbx) { @@ -967,59 +1167,69 @@ OP_IMPL(sbx) { /* sets b to b-a+EX, sets EX to 0xffff if underflow, 0x0 otherwise */ unsigned int acc; - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); - acc = *b - *a + d->ex; + ACCT_REG_R(DCPU16_REG_EX); + + acc = *b - *a + vm->reg[DCPU16_REG_EX]; *b = acc & 0xffff; if (acc > 0xffff) - d->ex = 0xffff; + vm->reg[DCPU16_REG_EX] = 0xffff; else - d->ex = 0; + vm->reg[DCPU16_REG_EX] = 0; + + ACCT_REG_W(DCPU16_REG_EX); - d->cycle += 3; + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 3); } OP_IMPL(sti) { OP_BASIC(sti); /* sets b to a, then increases I and J by 1 */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = *a; - d->reg[reg_index_('I')] += 1; - d->reg[reg_index_('J')] += 1; + vm->reg[DCPU16_REG_I] += 1; + vm->reg[DCPU16_REG_J] += 1; + + ACCT_REG_W(DCPU16_REG_I); + ACCT_REG_W(DCPU16_REG_J); - d->cycle += 2; + ACCT_W(b); - ACCT_W(ev_b_addr); + dcpu16_cycle_inc(vm, 2); } OP_IMPL(std) { OP_BASIC(std); /* sets b to a, then decreases I and J by 1 */ - ACCT_R(ev_b_addr); - ACCT_R(ev_a_addr); + ACCT_R(b); + ACCT_R(a); *b = *a; - d->reg[reg_index_('I')] -= 1; - d->reg[reg_index_('J')] -= 1; + vm->reg[DCPU16_REG_I] -= 1; + vm->reg[DCPU16_REG_J] -= 1; - d->cycle += 2; + ACCT_REG_W(DCPU16_REG_I); + ACCT_REG_W(DCPU16_REG_J); - ACCT_W(ev_b_addr); + ACCT_W(b); + + dcpu16_cycle_inc(vm, 2); } OP_IMPL(_reserved_) { OP_BASIC(_reserved_); - WARN("reserved opcode invoked"); + MSG_INFO(vm, "reserved opcode invoked"); - ACCT_ILL(d->pc - pc_adjust); + ACCT_ILL(vm->reg[DCPU16_REG_PC] - pc_adjust); } static const struct opcode_entry opcode_basic_entries[] = { @@ -1057,34 +1267,76 @@ static const struct opcode_entry opcode_basic_entries[] = { {0x1f, "STD", op_std }, {0x00, "", NULL } }; +#define OPCODE_BASIC_MAX (((sizeof(opcode_basic_entries)) / (sizeof(struct opcode_entry))) - 1) static inline void dump_operand_value_(DCPU16_WORD value, DCPU16_WORD nextword, unsigned int value_position) { + printf(" "); if (value <= 0x07) { - printf(" %c", regnames_[value]); + printf("%s", dcpu16_reg_names[value]); } else if (value <= 0x0f) { - printf(" [%c]", regnames_[value & 0x07]); + printf("[%s]", dcpu16_reg_names[value & 0x07]); } else if (value <= 0x17) { - printf(" [0x%04x + %c]", nextword, regnames_[value & 0x07]); + printf("[0x%04x + %s]", nextword, dcpu16_reg_names[value & 0x07]); } else switch (value) { case 0x18: if (value_position == 0) { /* b */ - printf(" PUSH"); + printf("PUSH"); } else { - printf(" POP"); + printf("POP"); } break; - case 0x19: printf(" PEEK"); break; - case 0x1a: printf(" PICK 0x%04x", nextword); break; - case 0x1b: printf(" SP"); break; - case 0x1c: printf(" PC"); break; - case 0x1d: printf(" EX"); break; - case 0x1e: printf(" [0x%04x]", nextword); break; - case 0x1f: printf(" 0x%04x", nextword); break; - default: printf(" 0x%02x", value - 0x21); + case 0x19: printf("PEEK"); break; + case 0x1a: printf("PICK 0x%04x", nextword); break; + case 0x1b: printf("SP"); break; + case 0x1c: printf("PC"); break; + case 0x1d: printf("EX"); break; + case 0x1e: printf("[0x%04x]", nextword); break; + case 0x1f: printf("0x%04x", nextword); break; + default: printf("0x%02x", value - 0x21); } } +static inline +int operand_snprint_(char *buf, size_t buf_sz, DCPU16_WORD value, DCPU16_WORD nextword, unsigned int operand_is_a) { + int len; + + len = snprintf(buf, buf_sz, " "); + if ((size_t)len >= buf_sz) + return -1; + + buf += len, buf_sz -= len; + + if (value <= 0x07) { + len = snprintf(buf, buf_sz, "%s", dcpu16_reg_names[value]); + } else if (value <= 0x0f) { + len = snprintf(buf, buf_sz, "[%s]", dcpu16_reg_names[value & 0x07]); + } else if (value <= 0x17) { + len = snprintf(buf, buf_sz, "[0x%04x + %s]", nextword, dcpu16_reg_names[value & 0x07]); + } else switch (value) { + case 0x18: + if (operand_is_a == 0) { /* b */ + len = snprintf(buf, buf_sz, "PUSH"); + } else { + len = snprintf(buf, buf_sz, "POP"); + } + break; + case 0x19: len = snprintf(buf, buf_sz, "PEEK"); break; + case 0x1a: len = snprintf(buf, buf_sz, "PICK 0x%04x", nextword); break; + case 0x1b: len = snprintf(buf, buf_sz, "SP"); break; + case 0x1c: len = snprintf(buf, buf_sz, "PC"); break; + case 0x1d: len = snprintf(buf, buf_sz, "EX"); break; + case 0x1e: len = snprintf(buf, buf_sz, "[0x%04x]", nextword); break; + case 0x1f: len = snprintf(buf, buf_sz, "0x%04x", nextword); break; + default: len = snprintf(buf, buf_sz, "0x%02x", (short)(value - 0x21)); + } + + if ((size_t)len >= buf_sz) + return -1; + + return len; +} + /* split a sequence of (one to three) words into the components of an instruction */ static inline @@ -1097,9 +1349,9 @@ void instruction_decode_(DCPU16_WORD *mem, DCPU16_WORD addr, *a = (mem[addr] >> (OPCODE_BASIC_BITS + OPCODE_OPERAND_B_BITS)) & ((1 << OPCODE_OPERAND_A_BITS) - 1); *instr_len = 1; - if ( (*b >= 0x10 && *b <= 0x17) || *b == 0x1e || *b == 0x1f ) { + if ((*opcode != 0x0000) && + ( (*b >= 0x10 && *b <= 0x17) || *b == 0x1e || *b == 0x1f ) ) { *b_data = mem + (DCPU16_WORD)(addr + *instr_len); - TRACE("**b_data:%hu", **b_data); *instr_len += 1; } else { *b_data = NULL; @@ -1108,14 +1360,13 @@ void instruction_decode_(DCPU16_WORD *mem, DCPU16_WORD addr, if ( (*opcode != 0x0000 || (*opcode == 0 && *b != 0x0000) ) && ( (*a >= 0x10 && *a <= 0x17) || *a == 0x1e || *a == 0x1f) ) { *a_data = mem + (DCPU16_WORD)(addr + *instr_len); - TRACE("**a_data:%hu", **a_data); *instr_len += 1; } else { *a_data = NULL; } -#if 0 - TRACE("\n%s: [0x%04x]:0x%04x op:0x%02x b:0x%02x (b_data:0x%04x) a:0x%02x (a_data:0x%04x) len:0x%02x\n", +#ifdef DEBUG_DECODE + MSG_(MSG_DEBUG_DECODE, NULL, "\n%s: [0x%04x]:0x%04x op:0x%02x b:0x%02x (b_data:0x%04x) a:0x%02x (a_data:0x%04x) len:0x%02x\n", __func__, addr, mem[addr], @@ -1125,7 +1376,7 @@ void instruction_decode_(DCPU16_WORD *mem, DCPU16_WORD addr, *a, *a_data ? **a_data : 0, *instr_len); -#endif +#endif /* DEBUG_DECODE */ } /* dcpu16_mnemonify_buf @@ -1134,6 +1385,7 @@ void instruction_decode_(DCPU16_WORD *mem, DCPU16_WORD addr, DCPU16_WORD dcpu16_mnemonify_buf(DCPU16_WORD *buf) { DCPU16_WORD opcode, b, a, instr_len, *b_data, *a_data; const struct opcode_entry *e; + char operand[16]; instruction_decode_(buf, 0, &opcode, &b, &b_data, &a, &a_data, &instr_len); @@ -1145,12 +1397,13 @@ DCPU16_WORD dcpu16_mnemonify_buf(DCPU16_WORD *buf) { printf("%s", e->name); if (opcode) { - dump_operand_value_(b, b_data ? *b_data : 0, 0); - printf(","); + operand_snprint_(operand, sizeof operand, b, b_data ? *b_data : 0, 0); + printf("%s,", operand); } if (opcode || b) { - dump_operand_value_(a, a_data ? *a_data : 0, 1); + operand_snprint_(operand, sizeof operand, a, a_data ? *a_data : 0, 1); + printf("%s", operand); } return instr_len; @@ -1160,13 +1413,13 @@ DCPU16_WORD dcpu16_mnemonify_buf(DCPU16_WORD *buf) { print the words of the instruction at addr, followed by its assembly representation returns the length of the instruction in words */ -DCPU16_WORD dcpu16_disassemble_print(struct dcpu16 *d, DCPU16_WORD addr) { +DCPU16_WORD dcpu16_disassemble_print(struct dcpu16 *vm, DCPU16_WORD addr) { DCPU16_WORD opcode, b, a, instr_len, i, *b_data, *a_data; - DCPU16_WORD buf[3] = { d->ram[addr], d->ram[(DCPU16_WORD)(addr + 1)], d->ram[(DCPU16_WORD)(addr + 2)] }; + DCPU16_WORD buf[3] = { vm->ram[addr], vm->ram[(DCPU16_WORD)(addr + 1)], vm->ram[(DCPU16_WORD)(addr + 2)] }; unsigned int indent = 0; unsigned int partial = 0; - if (!d) return 0; + if (!vm) return 0; #if 0 /* @@ -1175,7 +1428,7 @@ DCPU16_WORD dcpu16_disassemble_print(struct dcpu16 *d, DCPU16_WORD addr) { could be data which happen to match instructions.. */ for (i = 3; i; i--) { - instruction_decode_(d->ram, (DCPU16_WORD)(addr - i), &opcode, &b, &b_data, &a, &a_data, &instr_len); + instruction_decode_(vm->ram, (DCPU16_WORD)(addr - i), &opcode, &b, &b_data, &a, &a_data, &instr_len); if (instr_len > i) partial++; if (instr_len == i @@ -1187,12 +1440,12 @@ DCPU16_WORD dcpu16_disassemble_print(struct dcpu16 *d, DCPU16_WORD addr) { #endif /* just need instr_len */ - instruction_decode_(d->ram, addr, &opcode, &b, &b_data, &a, &a_data, &instr_len); + instruction_decode_(vm->ram, addr, &opcode, &b, &b_data, &a, &a_data, &instr_len); /* show the raw words */ - printf("%04x", d->ram[addr]); + printf("%04x", vm->ram[addr]); for (i = 1; i < instr_len; i++) { - printf(" %04x", d->ram[addr + i]); + printf(" %04x", vm->ram[addr + i]); } /* align things neatly, show the instruction */ @@ -1207,123 +1460,164 @@ DCPU16_WORD dcpu16_disassemble_print(struct dcpu16 *d, DCPU16_WORD addr) { return instr_len; } +int dcpu16_interrupt(struct dcpu16 *vm, DCPU16_WORD message) { + MSG_DEBUG(vm, "%s>> message:0x%04x", __func__, message); + return interrupt_enqueue_(vm, message); +} + /* execute the next instruction */ -void dcpu16_step(struct dcpu16 *d) { +void dcpu16_step(struct dcpu16 *vm) { DCPU16_WORD opcode, b, a, instr_len, *b_data, *a_data; const struct opcode_entry *e; - if (!d) return; + if (!vm) + return; + + instruction_decode_(vm->ram, vm->reg[DCPU16_REG_PC], &opcode, &b, &b_data, &a, &a_data, &instr_len); + + /* consume what we decoded */ + /* this happens immediately as PC might be re-set as an operation */ + vm->reg[DCPU16_REG_PC] += instr_len; + + /* run the operation */ + e = opcode_basic_entries + opcode; + MSG_DEBUG(vm, "%s", e->name ? e->name : "???"); + e->impl(vm, b, b_data ? *b_data : 0, a, a_data ? *a_data : 0); - acct_event_(d, DCPU16_ACCT_EV_CYCLE, d->pc); + + /* and jump over next instr(s) if needed */ + while (vm->skip_) { + instruction_decode_(vm->ram, vm->reg[DCPU16_REG_PC], &opcode, &b, &b_data, &a, &a_data, &instr_len); + vm->reg[DCPU16_REG_PC] += instr_len; + MSG_DEBUG(vm, "%s>> ++ SKIPPED %x words", __func__, instr_len); + if (opcode >= 0x10 && opcode <= 0x17) { + /* skipping a branch instruction? skip branch's skippable instruction as well */ + dcpu16_cycle_inc(vm, 1); + } else { + vm->skip_ = 0; + } + } /* if we're currently servicing interrupts */ - if (d->interrupts_deferred_ == 0) { + if (vm->interrupts_deferred_ == 0) { /* and there are interrupts to be serviced */ - if (d->interrupts_head_ != d->interrupts_tail_) { + if (vm->interrupts_head_ != vm->interrupts_tail_) { DCPU16_WORD message; - message = interrupt_dequeue_(d); + message = interrupt_dequeue_(vm); + + MSG_DEBUG(vm, "%s>> %s interrupt IA:0x%04x message:0x%04x", + __func__, + vm->reg[DCPU16_REG_IA] ? "servicing" : "ignoring", + vm->reg[DCPU16_REG_IA], + message); - if (d->ia) { - TRACE("servicing interrupt IA:0x%04x message:0x%04x \n", d->ia, message); + if (vm->reg[DCPU16_REG_IA]) { /* then service the next interrupt */ - d->interrupts_deferred_ = 1; - d->ram[--d->sp] = d->pc; - d->ram[--d->sp] = d->reg[reg_index_('A')]; - d->pc = d->ia; - d->reg[0] = message; - } else { - TRACE("ignoring interrupt IA:0"); + vm->interrupts_deferred_ = 1; + vm->ram[--vm->reg[DCPU16_REG_SP]] = vm->reg[DCPU16_REG_PC]; + vm->ram[--vm->reg[DCPU16_REG_SP]] = vm->reg[DCPU16_REG_A]; + vm->reg[DCPU16_REG_PC] = vm->reg[DCPU16_REG_IA]; + vm->reg[DCPU16_REG_A] = message; } } } +} - /* and make sure to execute an instruction after an interrupt */ - instruction_decode_(d->ram, d->pc, &opcode, &b, &b_data, &a, &a_data, &instr_len); +/* instantiate a new 'hardware' device */ +struct dcpu16_hw *dcpu16_hw_new(struct dcpu16 *vm, struct dcpu16_hw_module *mod, void *data) { + struct dcpu16_hw *hw; - for (e = opcode_basic_entries; e->impl; e++) { - if (e->value == opcode) { - TRACE("%s>> %s 0x%04x, 0x%04x", __func__, e->name, b, a); - e->impl(d, b, b_data ? *b_data : 0, a, a_data ? *a_data : 0); - break; - } - } - - /* get ready for the next one */ - d->pc += instr_len; + MSG_DEBUG(vm, "%s>> mod:%p data:%p", __func__, mod, data); - /* and jump over next instr(s) if needed */ - if (d->skip_) { - instruction_decode_(d->ram, d->pc, &opcode, &b, &b_data, &a, &a_data, &instr_len); - d->pc += instr_len; - TRACE("++ SKIPPED %x words", instr_len); - if (opcode >= 0x10 && opcode <= 0x17) { - /* skipping a branch instruction? skip branch's skippable instruction as well */ - d->cycle += 1; - instruction_decode_(d->ram, d->pc, &opcode, &b, &b_data, &a, &a_data, &instr_len); - d->pc += instr_len; - TRACE("++ SKIPPED %x words", instr_len); + hw = malloc(sizeof *hw); + if (hw == NULL) { + MSG_ERROR(vm, "%s():%s", "malloc", strerror(errno)); + return NULL; + } + hw->vm = vm; + hw->mod = mod; + + if (mod->data_init) { + if (mod->data_init(hw, data)) { + MSG_ERROR(vm, "failed to init hw module data"); + free(hw); + return NULL; } - d->skip_ = 0; + } else { + hw->data = NULL; } -} - -/* - print the current state of the machine - shows current cycle count, registers, and next instruction -*/ -void dcpu16_state_print(struct dcpu16 *d) { - unsigned int i; - - if (!d) return; - printf(" "); - for (i = 0; i < 8; i++) - printf(" %c:0x%04x", regnames_[i], d->reg[i]); - printf("\n"); + return hw; +} - printf("(0x%08llx) %2s:0x%04x %2s:0x%04x %2s:0x%04x %2s:0x%04x [%2s]:", - d->cycle, - "EX", d->ex, - "SP", d->sp, - "PC", d->pc, - "IA", d->ia, - "PC"); +/* destroy a 'hardware' device */ +void dcpu16_hw_del(struct dcpu16_hw **hw) { + if (hw) { + if (*hw) { + MSG_DEBUG((*hw)->vm, "%s>> hw:%p", + __func__, + *hw); - dcpu16_disassemble_print(d, d->pc); - printf("\n"); + if ((*hw)->mod->data_free) { + (*hw)->mod->data_free(*hw); + } + free(*hw); + *hw = NULL; + } + } } -/* dcpu16_dump_ram - * print raw ram contents from start to stop +/* dcpu16_hw_ctl + * invokes per-module controls for hw device */ -void dcpu16_dump_ram(struct dcpu16 *d, DCPU16_WORD start, DCPU16_WORD end) { - unsigned int i, j; - const unsigned int n = 8; /* words per line */ - - if (!d) return; +int dcpu16_hw_ctl(struct dcpu16_hw *hw, const char *cmd, void *data_in, void *data_out) { + if (!hw) + return -1; - for (i = start, j = 0; i <= end; i++, j++) { - if (j % n == 0) - printf("0x%04x:\t", i); - printf(" %04x%s", d->ram[i], (j % n) == (n - 1) ? "\n" : ""); + MSG_DEBUG(hw->vm, "%s>> name:%s cmd:%s in:%p out:%p", + __func__, + hw->mod->name_, + cmd, + data_in, + data_out); + + if (hw->mod) { + if (hw->mod->ctl) { + if (cmd) { + return hw->mod->ctl(hw, cmd, data_in, data_out); + } + } } - if ((j % n) != (n - 1)) - printf("\n"); + + return 0; } -/* dcpu16_hw_add + +/* dcpu16_hw_attach * registers new 'hardware' device with system */ -int dcpu16_hw_add(struct dcpu16 *vm, struct dcpu16_hw *hw) { +int dcpu16_hw_attach(struct dcpu16 *vm, struct dcpu16_hw *hw) { if (!vm || !hw) return -1; + MSG_DEBUG(vm, "%s>> name:%s ID:0x%04x%04x MFG:0x%04x%04x VER:0x%04x", + __func__, + hw->mod->name_, + hw->mod->id_h, hw->mod->id_l, + hw->mod->mfg_l, hw->mod->mfg_h, + hw->mod->ver); + + if (vm->hw_table_entries_ == 0xffff) { + MSG_ERROR(vm, "maximum hardware entries reached"); + return -1; + } + if (vm->hw_table_entries_ == vm->hw_table_allocated_) { size_t new_entries = vm->hw_table_allocated_ + 32; void *tmp_ptr = realloc(vm->hw_table_, new_entries * sizeof * (vm->hw_table_)); if (tmp_ptr == NULL) { - fprintf(stderr, "%s():%s", "realloc", strerror(errno)); + MSG_ERROR(vm, "%s():%s", "realloc", strerror(errno)); return -1; } vm->hw_table_ = tmp_ptr; @@ -1333,6 +1627,8 @@ int dcpu16_hw_add(struct dcpu16 *vm, struct dcpu16_hw *hw) { memcpy(vm->hw_table_ + vm->hw_table_entries_, hw, sizeof *hw); vm->hw_table_entries_++; + MSG_DEBUG(vm, "%s>> added hw entry %zu", __func__, vm->hw_table_entries_); + return 0; } @@ -1340,10 +1636,21 @@ int dcpu16_hw_add(struct dcpu16 *vm, struct dcpu16_hw *hw) { * Register callback fn to be triggered whenever event matching any events * in bitwise mask occur. */ -int dcpu16_acct_add(struct dcpu16 *vm, dcpu16_acct_event mask, dcpu16_ev_cb_t *fn, void *data) { - struct dcpu16_acct_cb cb; +int dcpu16_acct_add(struct dcpu16 *vm, dcpu16_acct_event mask, dcpu16_ev_cb_t *fn, DCPU16_WORD addr_l, DCPU16_WORD addr_h, void *data) { + struct dcpu16_acct_cb cb = { + .mask = mask, + .addr_l = addr_l, + .addr_h = addr_h, + .fn = fn, + .data = data, + }; + + if (!vm) + return -1; cb.mask = mask; + cb.addr_l = addr_l; + cb.addr_h = addr_h; cb.fn = fn; cb.data = data; @@ -1351,7 +1658,7 @@ int dcpu16_acct_add(struct dcpu16 *vm, dcpu16_acct_event mask, dcpu16_ev_cb_t *f size_t new_entries = vm->cb_table_allocated_ + 32; void *tmp_ptr = realloc(vm->cb_table_, new_entries * sizeof *(vm->cb_table_)); if (tmp_ptr == NULL) { - fprintf(stderr, "%s():%s", "realloc", strerror(errno)); + MSG_ERROR(vm, "%s():%s", "realloc", strerror(errno)); return -1; } vm->cb_table_ = tmp_ptr; @@ -1361,25 +1668,40 @@ int dcpu16_acct_add(struct dcpu16 *vm, dcpu16_acct_event mask, dcpu16_ev_cb_t *f memcpy(vm->cb_table_ + vm->cb_table_entries_, &cb, sizeof cb); vm->cb_table_entries_++; + MSG_DEBUG(vm, "%s>> attached event callback %zu", __func__, vm->cb_table_entries_); + return 0; } /* dcpu16_reset * signals cpu to reset, clearing runstate and ram, then reload any init callbacks */ -void dcpu16_reset(struct dcpu16 *d) { - if (!d) return; +void dcpu16_reset(struct dcpu16 *vm) { + size_t i; + + if (!vm) + return; + + MSG_DEBUG(vm, "%s>> reset", __func__); - d->cycle = 0; - memset(d->reg, 0, sizeof d->reg); - d->pc = 0; - d->sp = 0; - d->ex = 0; - d->ia = 0; - d->skip_ = 0; - memset(d->ram, 0, sizeof d->ram); + vm->skip_ = 0; + vm->interrupts_deferred_ = 0; + vm->on_fire_ = 0; + memset(vm->interrupts_, 0, sizeof vm->interrupts_); + vm->interrupts_head_ = 0; + vm->interrupts_tail_ = 0; - acct_event_(d, DCPU16_ACCT_EV_RESET, 0); + /* signal attached hardware */ + for (i = 0; i < vm->hw_table_entries_; i++) { + if (vm->hw_table_[i].mod->reset) + vm->hw_table_[i].mod->reset(vm, &vm->hw_table_[i]); + } + + memset(vm->reg, 0, sizeof vm->reg); + memset(vm->ram, 0, sizeof vm->ram); + vm->cycle_ = 0; + + acct_event_(vm, DCPU16_ACCT_EV_RESET, 0); } /* dcpu16_new @@ -1390,7 +1712,9 @@ struct dcpu16 *dcpu16_new(void) { vm = calloc(1, sizeof *vm); if (vm == NULL) - WARN("%s: %s(%zu): %s", __func__, "calloc", strerror(errno)); + MSG_ERROR(NULL, "%s: %s(%zu): %s", __func__, "calloc", strerror(errno)); + + vm->msg_cb_ = dcpu16_msg_; return vm; } @@ -1399,7 +1723,8 @@ struct dcpu16 *dcpu16_new(void) { * release a dcpu16 instance */ void dcpu16_delete(struct dcpu16 **vm) { - if (!vm || !*vm) return; + if (!vm || !*vm) + return; free(*vm); *vm = NULL;